The present disclosure relates to analog-to-digital conversion. More specifically, the present disclosure relates to a system and method for using current mode sigma-delta modulators to provide efficient analog-to-digital conversion.
In digital image or video capturing systems, image sensors are used for converting light energy into electrical signals so that a digital representation may be obtained. A digital image sensor in such a system typically comprises a pixel array, a bank of sample-and-hold (SH) circuits, a bank of analog-to-digital converters (ADCs), readout circuits, timing circuits, and control circuits.
Depending on the particular application, various types of ADCs may be used in image sensors. These include flash ADCs, single-slope ADCs, successive approximation ADCs, pipelined ADCs, sigma-delta ADCs (also known as delta-sigma ADCs), and the like. Sigma-delta ADCs are often used because they can be constructed using simple circuit components, can achieve high output accuracy, and are suitable for implementation in large scale integrated circuits (such as an image sensor) where there are many ADCs operating in parallel. Using a large number of ADCs in parallel requires a circuit designer to ensure each of the ADCs have similar characteristics so that the resulting system is not subject to pattern noise as a result of, for example, circuit mismatches among the multiple ADCs.
Sigma-delta ADCs can be implemented in voltage mode or in current mode, both of which are often used in image sensors. Moreover, in image sensors, a column ADC architecture, where one ADC is provided for each column of a pixel array, is often used. In such a configuration, the pixels in each column are read out using parallel circuits on a row-by-row basis. Thus, the analog signal (whether voltage or current) representing the pixel values in each row of the sensor are fed into the ADCs in parallel to be converted into a row of corresponding digital pixel values.
In its most basic form, a sigma-delta ADC includes a modulator and a decimation filter. The ADC operates at an oversampling ratio R, which may range into the hundreds. That is, the number of binary samples in the sigma-delta modulator of the ADC is R times the number of multi-bit out samples from the decimation filter of the ADC. A comparative example of a modulator used in such a form is illustrated in FIGS. 1-2.
FIG. 1 illustrates a current mode sigma-delta modulator 100 including an input node for an input current (represented by current source 111), a clocked comparator quantizer 101, a reference current source 112, a switch 121, and an integrating capacitor 131. When used in an image sensor, current source 111 represents an output analog signal from a pixel readout circuit having a current value Iin. Reference current source 112 outputs a reference current Iref. Comparator 101 is configured to compare a voltage Vint on capacitor 131 with a reference voltage Vref, and to output an output voltage Vout as a comparison result. Switch 121 is configured such that when the output of comparator 101 is at a high level, switch 121 is closed. Conversely, when the output of comparator 101 is at a low level, switch 121 is opened.
FIG. 2 illustrates the signals Vout and Vint of comparator 101, along with the clock signal CLK received by comparator 101. To ensure proper operation of the ADC, the circuit is set such that Iin<Iref. The initial state for illustration is one where Vint is at a low level, such that Vint<Vref. In this state, the output Vout is low, causing switch 121 to be open. Because switch 121 is open, capacitor 131 is charged by the input current Iin, and Vint rises as shown in FIG. 2. Eventually, Vint becomes higher than Vref which causes Vout to become high, in turn causing switch 121 to close. As illustrated in FIG. 2, Vout does not become high at the instant Vin crosses Vref. This is because comparator 101 operates under the control of a clock and is only capable of switching the output in synchronization with the clock signal.
Once output Vout does become high and switch 121 is closed, capacitor 131 is discharged by the current Iref−Iin. As a result of this discharging, Vint decreases until it becomes lower than Vref. When this happens, output Vout switches to the low state (after another delay due to the clocked nature of comparator 101) and the cycle repeats itself. Thus, the output of comparator 101 represents a bit stream that can be decoded to determine the value of Iin. As illustrated in FIG. 2, because of the overshoot caused by the clocked nature of comparator 101, Vint actually ranges from V1 to V2 where V1 is lower than Vref and V2 is higher than Vref.
Sigma-delta modulator 100 suffers from several drawbacks, however. For example, it is not robust against clock jitters. That is, comparator 101 operates synchronously with the clock signal to produce the output Vout and thus to control switch 121. When clock jitter exists, the charging and discharging times will vary as a result. The amount of variation is directly proportional to the amount of clock jitter because discharging of capacitor 131 is done using reference current source 112 having a constant reference current. Because the charging and discharging times directly affect the decoded output, clock jitter will result in output errors caused by modulator 100. This becomes especially important in an image sensor where many ADCs are provided in parallel. For example, routing a clock signal from one end of the sensor to another end of the sensor incurs a delay and thus introduces clock jitter among the ADCs. Therefore, the output from each ADC will be different. This results in a pattern noise in the output of the image sensor.
Attempts to correct these deficiencies have themselves resulted in new problems. One such problematic configuration that has been proposed is illustrated in FIG. 3 as sigma-delta modulator 300. Sigma-delta modulator 300 is similar to sigma-delta modulator 100 in that it includes an input node represented by current source 311, a comparator 301, a switch 321, and an integrating capacitor 331. However, this type of modulator does not work properly because the input current on capacitor 331 can be removed once an external driver 341 is connected. In other words, the external device, rather than the feedback circuit, can define the voltage on capacitor 331.
Accordingly, there exists a need for a sigma-delta modulator having improved robustness against clock jitter in an image sensor without using a reference current source or an external driver.